Field of the Disclosure
The present disclosure relates generally to processing systems and more particularly to memory access for processing systems.
Description of the Related Art
A processing system typically employs random access memory (RAM) to store data used for processing operations. The memory has a plurality of entries (e.g. rows or lines), whereby each entry includes a set of bit cells to store the individual bits of the entry. In response to a read access request, the processing system can read data from an entry using a read operation having two phases: a precharge phase and an evaluate phase. During the precharge phase, the memory precharges bitlines for the memory bitcells to a defined voltage representing an asserted logic level (e.g. a logic value of “1”). During the evaluate phase, the memory stops precharging of the bitcells of the entry to be read, so that the bitlines connected to the bitcells are each set to a voltage level representing the data stored at their corresponding bit cell.
During the evaluate phase of a read operation, precharging of the bitlines of the entry to be read (referred to for purposes of description as “read bitlines”) must be terminated. However, for some types of memories it is necessary to maintain, during the evaluate phase, precharging of bitlines for bitcells that are not the subject of the read operation (referred to for purposes of description as “non-read bitlines”). For example, some memories logically combine bitlines of different memory entries during the evaluate phase in order to output each bit of the data being read. The logical combination is such that it outputs a correct result (i.e. the output of the logical combination correctly represents a bit of the data to be read) if the bitlines for all of the entries that are not being read are maintained at a precharge level. That is, if the bitlines for the entries that are not being read are not kept at the precharge level during the evaluate phase, it substantially increases the likelihood of an error in the data being read. Accordingly, during the evaluate phase it is useful to terminate precharging only for the bitlines of the read bitcells. In some systems, this is done by generating a precharge disable signal by logically ORing (combining using an OR operation) read wordlines of a group of memory entries, including the read entry, together. However, this technique can cause delays in completing the read operation.